Jhih-Yu Jiang, Ping-Chuan Chiang, Hao-Wei Hung, Chen-Lun Lin, Ty Yoon, Jri Lee. 100Gb/s ethernet chipsets in 65nm CMOS technology. In 2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013. pages 120-121, IEEE, 2013. [doi]
@inproceedings{JiangCHLYL13,
title = {100Gb/s ethernet chipsets in 65nm CMOS technology},
author = {Jhih-Yu Jiang and Ping-Chuan Chiang and Hao-Wei Hung and Chen-Lun Lin and Ty Yoon and Jri Lee},
year = {2013},
doi = {10.1109/ISSCC.2013.6487663},
url = {http://dx.doi.org/10.1109/ISSCC.2013.6487663},
researchr = {https://researchr.org/publication/JiangCHLYL13},
cites = {0},
citedby = {0},
pages = {120-121},
booktitle = {2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013},
publisher = {IEEE},
isbn = {978-1-4673-4515-6},
}