Shan Jiang, Manh Anh Do, Kiat Seng Yeo. A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs. In IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006. pages 352-356, IEEE, 2006. [doi]
Abstract is missing.