Timing Macro Modeling for Efficient Hierarchical Timing Analysis

Iris Hui-Ru Jiang, Pei-Yu Lee. Timing Macro Modeling for Efficient Hierarchical Timing Analysis. In 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018. pages 714, IEEE Computer Society, 2018. [doi]

Authors

Iris Hui-Ru Jiang

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Pei-Yu Lee

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