A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic

Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji. A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic. In ICCD. pages 276-281, 1998. [doi]

@inproceedings{JiangSB98,
  title = {A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic},
  author = {Yanbin Jiang and Sachin S. Sapatnekar and Cyrus Bamji},
  year = {1998},
  doi = {10.1109/ICCD.1998.727062},
  url = {http://doi.ieeecomputersociety.org/10.1109/ICCD.1998.727062},
  researchr = {https://researchr.org/publication/JiangSB98},
  cites = {0},
  citedby = {0},
  pages = {276-281},
  booktitle = {ICCD},
}