Luo Jianwen, Jong Ching Chuen. Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAs. In 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France. pages 244-248, IEEE Computer Society, 2004. [doi]
Abstract is missing.