7.2 A 12nm Programmable Convolution-Efficient Neural-Processing-Unit Chip Achieving 825TOPS

Yang Jiao, Liang Han, Rong Jin, Yi-Jung Su, Chiente Ho, Li Yin, Yun Li, Long Chen, Zhen Chen, Lu Liu, Zhuyu He, Yu Yan, Jun He, Jun Mao, Xiaotao Zai, Xuejun Wu, Yongquan Zhou, Mingqiu Gu, Guocai Zhu, Rong Zhong, Wenyuan Lee, Ping Chen, Yiping Chen, Weiliang Li, Deyu Xiao, Qing Yan, Mingyuan Zhuang, Jiejun Chen, Yun Tian, Yingzi Lin, Wei Wu, Hao Li, Zesheng Dou. 7.2 A 12nm Programmable Convolution-Efficient Neural-Processing-Unit Chip Achieving 825TOPS. In 2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020. pages 136-140, IEEE, 2020. [doi]

@inproceedings{JiaoHJSHYLCCLHY20,
  title = {7.2 A 12nm Programmable Convolution-Efficient Neural-Processing-Unit Chip Achieving 825TOPS},
  author = {Yang Jiao and Liang Han and Rong Jin and Yi-Jung Su and Chiente Ho and Li Yin and Yun Li and Long Chen and Zhen Chen and Lu Liu and Zhuyu He and Yu Yan and Jun He and Jun Mao and Xiaotao Zai and Xuejun Wu and Yongquan Zhou and Mingqiu Gu and Guocai Zhu and Rong Zhong and Wenyuan Lee and Ping Chen and Yiping Chen and Weiliang Li and Deyu Xiao and Qing Yan and Mingyuan Zhuang and Jiejun Chen and Yun Tian and Yingzi Lin and Wei Wu and Hao Li and Zesheng Dou},
  year = {2020},
  doi = {10.1109/ISSCC19947.2020.9062984},
  url = {https://doi.org/10.1109/ISSCC19947.2020.9062984},
  researchr = {https://researchr.org/publication/JiaoHJSHYLCCLHY20},
  cites = {0},
  citedby = {0},
  pages = {136-140},
  booktitle = {2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020},
  publisher = {IEEE},
  isbn = {978-1-7281-3205-1},
}