Improving the Hardware Utilization Efficiency of Partially Parallel LDPC Decoder with Scheduling and Sub-matrix Decomposition - researchr publication authors

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Jie Jin, Chi-Ying Tsui. Improving the Hardware Utilization Efficiency of Partially Parallel LDPC Decoder with Scheduling and Sub-matrix Decomposition. In International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan. pages 2233-2236, IEEE, 2009. [doi]

This author has not been identified. Look up 'Jie Jin' in GoogleThis author has not been identified. Look up 'Chi-Ying Tsui' in Google

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