Jie Jin, Chi-Ying Tsui. Improving the Hardware Utilization Efficiency of Partially Parallel LDPC Decoder with Scheduling and Sub-matrix Decomposition. In International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan. pages 2233-2236, IEEE, 2009. [doi]
@inproceedings{JinT09-1,
title = {Improving the Hardware Utilization Efficiency of Partially Parallel LDPC Decoder with Scheduling and Sub-matrix Decomposition},
author = {Jie Jin and Chi-Ying Tsui},
year = {2009},
doi = {10.1109/ISCAS.2009.5118242},
url = {http://dx.doi.org/10.1109/ISCAS.2009.5118242},
researchr = {https://researchr.org/publication/JinT09-1},
cites = {0},
citedby = {0},
pages = {2233-2236},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan},
publisher = {IEEE},
}