Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs - researchr publication authors

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Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar Iyer, Chita R. Das. Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs. In Patrick Groeneveld, Donatella Sciuto, Soha Hassoun, editors, The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012. pages 243-252, ACM, 2012. [doi]

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