Tim Johnson, Umesh Nawathe. An 8-core, 64-thread, 64-bit power efficient sparc soc (niagara2). In Patrick H. Madden, David Z. Pan, editors, Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007. pages 2, ACM, 2007. [doi]
Abstract is missing.