Speeding up Quantified Bit-Vector SMT Solvers by Bit-Width Reductions and Extensions

Martin Jonás, Jan Strejcek. Speeding up Quantified Bit-Vector SMT Solvers by Bit-Width Reductions and Extensions. In Luca Pulina, Martina Seidl, editors, Theory and Applications of Satisfiability Testing - SAT 2020 - 23rd International Conference, Alghero, Italy, July 3-10, 2020, Proceedings. Volume 12178 of Lecture Notes in Computer Science, pages 378-393, Springer, 2020. [doi]

Abstract

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