Amit M. Joshi, Mohd. Samar Ansari, Chitrakant Sahu. VLSI Architecture of High Speed SAD for High Efficiency Video Coding (HEVC) Encoder. In IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy. pages 1-4, IEEE, 2018. [doi]
Abstract is missing.