Rathin Joshi, Rutu Parekh, Yash Agrawal. Design and Optimization of Single Electron Transistor Based 4-Bit Arithmetic and Logic Unit at Room Temperature Operation. In IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017, Bhopal, India, December 18-20, 2017. pages 34-39, IEEE, 2017. [doi]
@inproceedings{JoshiPA17,
title = {Design and Optimization of Single Electron Transistor Based 4-Bit Arithmetic and Logic Unit at Room Temperature Operation},
author = {Rathin Joshi and Rutu Parekh and Yash Agrawal},
year = {2017},
doi = {10.1109/iNIS.2017.17},
url = {http://doi.ieeecomputersociety.org/10.1109/iNIS.2017.17},
researchr = {https://researchr.org/publication/JoshiPA17},
cites = {0},
citedby = {0},
pages = {34-39},
booktitle = {IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017, Bhopal, India, December 18-20, 2017},
publisher = {IEEE},
isbn = {978-1-5386-1356-6},
}