Rathin Joshi, Rutu Parekh, Yash Agrawal. Design and Optimization of Single Electron Transistor Based 4-Bit Arithmetic and Logic Unit at Room Temperature Operation. In IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017, Bhopal, India, December 18-20, 2017. pages 34-39, IEEE, 2017. [doi]
Abstract is missing.