CACTI-IO: CACTI with off-chip power-area-timing models

Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas. CACTI-IO: CACTI with off-chip power-area-timing models. In 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012. pages 294-301, IEEE, 2012. [doi]

@inproceedings{JouppiKMS12,
  title = {CACTI-IO: CACTI with off-chip power-area-timing models},
  author = {Norman P. Jouppi and Andrew B. Kahng and Naveen Muralimanohar and Vaishnav Srinivas},
  year = {2012},
  url = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6386626},
  researchr = {https://researchr.org/publication/JouppiKMS12},
  cites = {0},
  citedby = {0},
  pages = {294-301},
  booktitle = {2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012},
  publisher = {IEEE},
}