Seobin Jung, Jiho Lee, Jaeha Kim. Yield-Aware Pareto Front Extraction for Discrete Hierarchical Optimization of Analog Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 33(10):1437-1449, 2014. [doi]
@article{JungLK14a,
title = {Yield-Aware Pareto Front Extraction for Discrete Hierarchical Optimization of Analog Circuits},
author = {Seobin Jung and Jiho Lee and Jaeha Kim},
year = {2014},
doi = {10.1109/TCAD.2014.2331563},
url = {http://dx.doi.org/10.1109/TCAD.2014.2331563},
researchr = {https://researchr.org/publication/JungLK14a},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {33},
number = {10},
pages = {1437-1449},
}