A parallel elliptic curve crypto-processor architecture with reduced clock cycle for FPGA platforms - researchr publication

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Murugesan Kalaiarasi, Vepadappu Raman Venkatasubramani, V. Vinoth Thyagarajan, S. Rajaram 0001. A parallel elliptic curve crypto-processor architecture with reduced clock cycle for FPGA platforms. The Journal of Supercomputing, 78(13):15567-15597, 2022. [doi]

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