Design guidelines for the high-speed dynamic partial reconfiguration based software defined radio implementations on Xilinx Zynq FPGA - researchr publication related

researchr

You are not signed in
Sign in
Sign up

Ahmed Kamaleldin, Ahmed M. Soliman, Ahmed Nagy, Youssef Gamal, Ahmed Shalash, Yehea Ismail, Hassan Mostafa. Design guidelines for the high-speed dynamic partial reconfiguration based software defined radio implementations on Xilinx Zynq FPGA. In IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017. pages 1-4, IEEE, 2017. [doi]

The following publications are possibly variants of this publication:

A reconfigurable hardware platform implementation for software defined radio using dynamic partial reconfiguration on Xilinx Zynq FPGAAhmed Kamaleldin, Sherif Hosny, Khaled Mohamed, Mostafa Gamal, Abdelrhman Hussien, Eslam Elnader, Ahmed Shalash, Abdelfattah Mohammad Obeid, Yehea Ismail, Hassan Mostafa. mwscas 2017: 1540-1543 [doi]

Performance evaluation of dynamic partial reconfiguration techniques for software defined radio implementation on FPGAAmr Hassan, Ramy Ahmed, Hassan Mostafa, Hossam A. H. Fahmy, Ahmed Hussien. icecsys 2015: 183-186 [doi]

A Cost-Effective Dynamic Partial Reconfiguration Implementation Flow for Xilinx FPGAAhmed Kamaleldin, Islam Ahmed, Abdulfattah Mohammad Obeid, Ahmed Shalash, Yehea Ismail, Hassan Mostafa. ngcas 2017: 281-284 [doi]

Complete Security Stack FPGA Implementation of The Software Defined Radio on ZYNQAbdelrhman M. Abotaleb, Abdulkareem M. Abotaleb, Amr G. Wassal, Hassan Mostafa. mwscas 2019: 864-867 [doi]

runs on WebDSL