A Translator from FDL to SystemVerilog for FPGA Implementation of Fuzzy Inference - researchr publication authors

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Yuichi Kamina, Keisuke Iwai, Takashi Matsubara 0002, Takakazu Kurokawa. A Translator from FDL to SystemVerilog for FPGA Implementation of Fuzzy Inference. In Eighth International Symposium on Computing and Networking Workshops, CANDAR 2020 Workshops, Naha, Japan, November 24-27, 2020. pages 87-92, IEEE, 2020. [doi]

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