A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS - researchr publication authors

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Raviteja Kammari, Vijaya Sankara Rao Pasupureddi. A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS. In Anirban Sengupta, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma, editors, VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers. Volume 1066 of Communications in Computer and Information Science, pages 202-214, Springer, 2019. [doi]

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