A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck

Toshiki Kanamoto, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Koki Kasai, Atsushi Kurokawa, Masashi Imai. A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck. In Hoi Lee, Randall L. Geiger, editors, 62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019, Dallas, TX, USA, August 4-7, 2019. pages 1085-1088, IEEE, 2019. [doi]

Abstract

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