Concurrent cell generation and mapping for CMOS logic circuits

M. Kanecko, Jialin Tian. Concurrent cell generation and mapping for CMOS logic circuits. In Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997. pages 247-252, IEEE, 1997. [doi]

Abstract

Abstract is missing.