Jihyo Kang, Jaehyeok Yang, Kyunghoon Kim, Joo-Hyung Chae, Gang-Sik Lee, Sang-Yeon Byeon, Boram Kim, Dong-hyun Kim, Youngtaek Kim, Yeongmuk Cho, Junghwan Ji, Sera Jeong, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Sunho Kim, Hae Kang Jung, Jieun Jang, Sangkwon Lee, Hyungsoo Kim, Joo-Hwan Cho, Junhyun Chun, Seon-Yong Cha. A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation. J. Solid-State Circuits, 57(1):212-223, 2022. [doi]
@article{KangYKCLBKKKCJJ22,
title = {A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation},
author = {Jihyo Kang and Jaehyeok Yang and Kyunghoon Kim and Joo-Hyung Chae and Gang-Sik Lee and Sang-Yeon Byeon and Boram Kim and Dong-hyun Kim and Youngtaek Kim and Yeongmuk Cho and Junghwan Ji and Sera Jeong and Jaehoon Cha and Minsoo Park and Hongdeuk Kim and Sijun Park and Sunho Kim and Hae Kang Jung and Jieun Jang and Sangkwon Lee and Hyungsoo Kim and Joo-Hwan Cho and Junhyun Chun and Seon-Yong Cha},
year = {2022},
doi = {10.1109/JSSC.2021.3114205},
url = {https://doi.org/10.1109/JSSC.2021.3114205},
researchr = {https://researchr.org/publication/KangYKCLBKKKCJJ22},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {57},
number = {1},
pages = {212-223},
}