High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4

Per Karlström, Andreas Ehliar, Dake Liu. High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4. IET Computers & Digital Techniques, 2(4):305-313, 2008. [doi]

@article{KarlstromEL08,
  title = {High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4},
  author = {Per Karlström and Andreas Ehliar and Dake Liu},
  year = {2008},
  doi = {10.1049/iet-cdt:20070075},
  url = {http://dx.doi.org/10.1049/iet-cdt:20070075},
  tags = {rule-based},
  researchr = {https://researchr.org/publication/KarlstromEL08},
  cites = {0},
  citedby = {0},
  journal = {IET Computers & Digital Techniques},
  volume = {2},
  number = {4},
  pages = {305-313},
}