Implementation of a high-speed low-power 32-bit adder in 70nm technology

F. Kashfi, Seid Mehdi Fakhraie. Implementation of a high-speed low-power 32-bit adder in 70nm technology. In International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [doi]

Authors

F. Kashfi

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Seid Mehdi Fakhraie

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