Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine. A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic. In IEEE 13th International New Circuits and Systems Conference, NEWCAS 2015, Grenoble, France, June 7-10, 2015. pages 1-4, IEEE, 2015. [doi]
Abstract is missing.