Sarang Kazeminia, Maryam Ghafoorzadeh, Faeze Noruzpur. An extendable global clock high-speed binary counter compatible to the FPGA CLBs. In 24th International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2017, Bydgoszcz, Poland, June 22-24, 2017. pages 220-223, IEEE, 2017. [doi]
@inproceedings{KazeminiaGN17,
title = {An extendable global clock high-speed binary counter compatible to the FPGA CLBs},
author = {Sarang Kazeminia and Maryam Ghafoorzadeh and Faeze Noruzpur},
year = {2017},
doi = {10.23919/MIXDES.2017.8005187},
url = {https://doi.org/10.23919/MIXDES.2017.8005187},
researchr = {https://researchr.org/publication/KazeminiaGN17},
cites = {0},
citedby = {0},
pages = {220-223},
booktitle = {24th International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2017, Bydgoszcz, Poland, June 22-24, 2017},
publisher = {IEEE},
isbn = {978-83-63578-12-1},
}