GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process - researchr publication authors

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Jhih-Ying Ke, Lean Karlo Santos Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang. GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process. In 6th IEEE International Conference on AI Circuits and Systems, AICAS 2024, Abu Dhabi, United Arab Emirates, April 22-25, 2024. pages 95-99, IEEE, 2024. [doi]

This author has not been identified. Look up 'Jhih-Ying Ke' in GoogleThis author has not been identified. Look up 'Lean Karlo Santos Tolentino' in GoogleThis author has not been identified. Look up 'Cheng-Yao Lo' in GoogleThis author has not been identified. Look up 'Tzung-Je Lee' in GoogleThis author has not been identified. Look up 'Chua-Chin Wang' in Google

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