Scalability Analysis for Conservative Simulation of Logical Circuits

Jörg Keller 0001, Thomas Rauber, Bernd Rederlechner. Scalability Analysis for Conservative Simulation of Logical Circuits. VLSI Design, 1999(3):219-235, 1999. [doi]

Authors

Jörg Keller 0001

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Thomas Rauber

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Bernd Rederlechner

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