Jörg Keller 0001, Thomas Rauber, Bernd Rederlechner. Scalability Analysis for Conservative Simulation of Logical Circuits. VLSI Design, 1999(3):219-235, 1999. [doi]
@article{KellerRR99,
title = {Scalability Analysis for Conservative Simulation of Logical Circuits},
author = {Jörg Keller 0001 and Thomas Rauber and Bernd Rederlechner},
year = {1999},
doi = {10.1155/1999/14802},
url = {https://doi.org/10.1155/1999/14802},
researchr = {https://researchr.org/publication/KellerRR99},
cites = {0},
citedby = {0},
journal = {VLSI Design},
volume = {1999},
number = {3},
pages = {219-235},
}