Igor Keller, King Ho Tam, Vinod Kariat. Challenges in gate level modeling for delay and SI at 65nm and below. In Limor Fix, editor, Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008. pages 468-473, ACM, 2008. [doi]
Abstract is missing.