Ming-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang. On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process. In International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan. pages 2281-2284, IEEE, 2009. [doi]
@inproceedings{KerCTC09,
title = {On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process},
author = {Ming-Dou Ker and Po-Yen Chiu and Fu-Yi Tsai and Yeong-Jar Chang},
year = {2009},
doi = {10.1109/ISCAS.2009.5118254},
url = {http://dx.doi.org/10.1109/ISCAS.2009.5118254},
tags = {design},
researchr = {https://researchr.org/publication/KerCTC09},
cites = {0},
citedby = {0},
pages = {2281-2284},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan},
publisher = {IEEE},
}