The following publications are possibly variants of this publication:
- Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technologyFederico A. Altolaguirre, Ming-Dou Ker. iscas 2013: 2638-2641 [doi]
- 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS processChun-Yu Lin, Ming-Dou Ker. iscas 2010: 3417-3420 [doi]
- Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS TechnologyChang-Tzu Wang, Ming-Dou Ker. jssc, 44(3):956-964, 2009. [doi]
- Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technologyFederico A. Altolaguirre, Ming-Dou Ker. vlsi-dat 2013: 1-4 [doi]
- New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS processChih-Ting Yeh, Ming-Dou Ker. vlsi-dat 2012: 1-4 [doi]
- Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-/spl mu/m silicide CMOS processMing-Dou Ker, Wen-Yu Lo. jssc, 35(4):601-611, 2000. [doi]
- Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuitPo-Yen Chiu, Ming-Dou Ker. mr, 54(1):64-70, 2014. [doi]
- Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technologyMing-Dou Ker, Wei-Jen Chang. mr, 47(1):27-35, 2007. [doi]
- New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS TechnologyChih-Ting Yeh, Ming-Dou Ker. tcas, 59-II(3):178-182, 2012. [doi]
- Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS processFederico A. Altolaguirre, Ming-Dou Ker. mwscas 2014: 250-253 [doi]
- Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS ProcessMing-Dou Ker, Wen-Yi Chen, Kuo-Chun Hsu. tcas, 53(10):2187-2193, 2006. [doi]