New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology

Chih-Ting Yeh, Ming-Dou Ker. New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology. IEEE Trans. on Circuits and Systems, 59-II(3):178-182, 2012. [doi]

Abstract

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