Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology

Chang-Tzu Wang, Ming-Dou Ker. Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology. J. Solid-State Circuits, 44(3):956-964, 2009. [doi]

Abstract

Abstract is missing.