Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process - researchr publication

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Ming-Dou Ker, Wen-Yi Chen, Kuo-Chun Hsu. Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process. IEEE Trans. on Circuits and Systems, 53(10):2187-2193, 2006. [doi]

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