Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

Ming-Dou Ker, Wen-Yi Chen, Kuo-Chun Hsu. Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process. IEEE Trans. on Circuits and Systems, 53(10):2187-2193, 2006. [doi]

Authors

Ming-Dou Ker

This author has not been identified. Look up 'Ming-Dou Ker' in Google

Wen-Yi Chen

This author has not been identified. Look up 'Wen-Yi Chen' in Google

Kuo-Chun Hsu

This author has not been identified. Look up 'Kuo-Chun Hsu' in Google