The following publications are possibly variants of this publication:
- Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technologyMing-Dou Ker, Wei-Jen Chang. mr, 47(1):27-35, 2007. [doi]
- On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS ProcessMing-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang. iscas 2009: 2281-2284 [doi]
- Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS processYuan-Wen Hsiao, Ming-Dou Ker. mr, 49(6):650-659, 2009. [doi]
- New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS TechnologyChih-Ting Yeh, Ming-Dou Ker. tcas, 59-II(3):178-182, 2012. [doi]
- Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS processFederico A. Altolaguirre, Ming-Dou Ker. mwscas 2014: 250-253 [doi]
- Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuitMing-Dou Ker, Chia-Sheng Tsai. iscas 2003: 97-100 [doi]
- Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-/spl mu/m silicide CMOS processMing-Dou Ker, Wen-Yu Lo. jssc, 35(4):601-611, 2000. [doi]
- New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS processChih-Ting Yeh, Ming-Dou Ker. vlsi-dat 2012: 1-4 [doi]
- ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS ProcessMing-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo. isqed 2002: 331-336 [doi]
- ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technologyMing-Dou Ker, Kun-Hsien Lin. jssc, 40(11):2329-2338, 2005. [doi]
- ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS processYuan-Wen Hsiao, Ming-Dou Ker, Po-Yen Chiu, Chun Huang, Yuh-Kuang Tseng. socc 2007: 277-280 [doi]
- Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on eventsChih-Ting Yeh, Yung-Chih Liang, Ming-Dou Ker. iscas 2011: 1403-1406 [doi]
- The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICsMing-Dou Ker, Kun-Hsien Lin. jssc, 40(8):1751-1759, 2005. [doi]
- Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS processChih-Ting Yeh, Ming-Dou Ker. vlsi-dat 2013: 1-4 [doi]