Avadhoot Khairnar, Bhavuk Chauhan, Geetanjali Sharma, Amit M. Joshi 0001. Erratum: High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic. Journal of Circuits, Systems, and Computers, 31(18), December 2022. [doi]
@article{KhairnarCSJ22a,
title = {Erratum: High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic},
author = {Avadhoot Khairnar and Bhavuk Chauhan and Geetanjali Sharma and Amit M. Joshi 0001},
year = {2022},
month = {December},
doi = {10.1142/S0218126622920013},
url = {https://doi.org/10.1142/S0218126622920013},
researchr = {https://researchr.org/publication/KhairnarCSJ22a},
cites = {0},
citedby = {0},
journal = {Journal of Circuits, Systems, and Computers},
volume = {31},
number = {18},
}