An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point Adder - researchr publication authors

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Nikhil Kikkeri, Peter-Michael Seidel. An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point Adder. In IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2007, Montréal, Québec, Canada, July 8-11, 2007. pages 83-88, IEEE Computer Society, 2007. [doi]

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