Nikhil Kikkeri, Peter-Michael Seidel. An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point Adder. In IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2007, Montréal, Québec, Canada, July 8-11, 2007. pages 83-88, IEEE Computer Society, 2007. [doi]
@inproceedings{KikkeriS07,
title = {An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point Adder},
author = {Nikhil Kikkeri and Peter-Michael Seidel},
year = {2007},
doi = {10.1109/ASAP.2007.4429962},
url = {http://dx.doi.org/10.1109/ASAP.2007.4429962},
researchr = {https://researchr.org/publication/KikkeriS07},
cites = {0},
citedby = {0},
pages = {83-88},
booktitle = {IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2007, Montréal, Québec, Canada, July 8-11, 2007},
publisher = {IEEE Computer Society},
}