Woo-Cheol Kim, Dong-Shin Jo, Yi-Ju Roh, Ye-Dam Kim, Seung-Tak Ryu. A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration. In 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019. pages 138, IEEE, 2019. [doi]
Abstract is missing.