A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers

Hyeonsik Kim, Soohoon Lee, Jintae Kim. A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers. IEEE Access, 11:22531-22541, 2023. [doi]

Abstract

Abstract is missing.