Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura. A novel power-gating scheme utilizing data retentiveness on caches. In Erik Brunvard, Ken Stevens, Joseph R. Cavallaro, Tong Zhang 0002, editors, Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake Cit, UT, USA, May 3-4, 2012. pages 91-94, ACM, 2012. [doi]
@inproceedings{KimTMN12,
title = {A novel power-gating scheme utilizing data retentiveness on caches},
author = {Kyundong Kim and Seidai Takeda and Shinobu Miwa and Hiroshi Nakamura},
year = {2012},
doi = {10.1145/2206781.2206805},
url = {http://doi.acm.org/10.1145/2206781.2206805},
researchr = {https://researchr.org/publication/KimTMN12},
cites = {0},
citedby = {0},
pages = {91-94},
booktitle = {Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake Cit, UT, USA, May 3-4, 2012},
editor = {Erik Brunvard and Ken Stevens and Joseph R. Cavallaro and Tong Zhang 0002},
publisher = {ACM},
isbn = {978-1-4503-1244-8},
}