A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network - researchr publication authors

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Kyunghoon Kim, SangSic Yoon, KiChang Kwean, DaeHan Kwon, SunSuk Yang, MunPhil Park, Yongki Kim, Byongtae Chung. A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network. In William Redman-White, Anthony J. Walton, editors, ESSCIRC 2008 - 34th European Solid-State Circuits Conference, Edinburgh, Scotland, UK, 15-19 September 2008. pages 194-197, IEEE, 2008. [doi]

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