A pipelined architecture for DLMS algorithm considering both hardware complexity and output latency - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Tadaaki Kimijima, Kiyoshi Nishikawa, Hitoshi Kiya. A pipelined architecture for DLMS algorithm considering both hardware complexity and output latency. In 9th European Signal Processing Conference, EUSIPCO 1998, Island of Rhodes, Greece, 8-11 September, 1998. pages 1-4, IEEE, 1998. [doi]

This author has not been identified. Look up 'Tadaaki Kimijima' in GoogleThis author has not been identified. Look up 'Kiyoshi Nishikawa' in GoogleThis author has not been identified. Look up 'Hitoshi Kiya' in Google

runs on WebDSL