Tadaaki Kimijima, Kiyoshi Nishikawa, Hitoshi Kiya. A pipelined architecture for DLMS algorithm considering both hardware complexity and output latency. In 9th European Signal Processing Conference, EUSIPCO 1998, Island of Rhodes, Greece, 8-11 September, 1998. pages 1-4, IEEE, 1998. [doi]
Abstract is missing.