Robert H. Klenke, Ronald D. Williams, James H. Aylor. Parallelization methods for circuit partitioning based parallel automatic test pattern generation. In 11th IEEE VLSI Test Symposium (VTS'93), 6 Apr 1993-8 Apr 1993, Atlantic City, NJ, USA. pages 71-78, IEEE, 1993. [doi]
No references recorded for this publication.
No citations of this publication recorded.