TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC - researchr publication authors

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Wolfgang Klingauf, Hagen Gädke, Robert Günzel. TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC. In Georges G. E. Gielen, editor, Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006. pages 1318-1323, European Design and Automation Association, Leuven, Belgium, 2006. [doi]

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