Layout engineering to suppress hysteresis of negative capacitance FinFET - researchr publication authors

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Eunah Ko, Jaesung Jo, Changhwan Shin, Bich-Yen Nguyen. Layout engineering to suppress hysteresis of negative capacitance FinFET. In 2017 IEEE International Conference on IC Design and Technology, ICICDT 2017, Austin, TX, USA, May 23-25, 2017. pages 1-3, IEEE, 2017. [doi]

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